The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Sep. 25, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Karthik Ramanan, Austin, TX (US);

Jon Scott Choy, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 11/1655 (2013.01); G11C 11/1659 (2013.01); G11C 11/1697 (2013.01); G11C 13/0026 (2013.01); G11C 2013/0054 (2013.01);
Abstract

A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.


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