The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2022
Filed:
Mar. 19, 2021
Cadence Design Systems, Inc., San Jose, CA (US);
Yanfei Shen, San Jose, CA (US);
Qingyu Lin, Pleasanton, CA (US);
Patrick O'Halloran, Santa Rosa, CA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
A method of reconstructing an emulated circuit layout for graphical display includes receiving a pre-layout circuit including one or more devices and one or more nodes. The method includes generating a Detailed Standard Parasitic Format (DPSF) netlist representing a post-layout circuit. The DPSF netlist includes a plurality of instances representing the one or more devices, the one or more nodes, and one or more parasitic elements not included in the pre-layout circuit. The method includes identifying at least one node of the one or more nodes that is associated with the one or more parasitic elements. The method includes updating the DPSF netlist to associate the one or more parasitic elements with the at least one node. The method includes constructing graphical representation of the post-layout circuit based on the updated DPSF netlist. The method includes causing a display device to display the graphical representation.