The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Dec. 30, 2019
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Liang Chen, Hubei, CN;

Lei Xue, Hubei, CN;

Wei Liu, Hubei, CN;

Shi Qi Huang, Hubei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 23/48 (2006.01); H01L 27/102 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 27/11531 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/481 (2013.01); H01L 27/1024 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11531 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01);
Abstract

A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.


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