The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Jan. 29, 2020
Applicant:

Amkor Technology Singapore Holding Pte. Ltd., Singapore OT, SG;

Inventors:

Ji Young Chung, Gyeonggi-Do, KR;

Seung Chul Jang, Jeollanam-do, KR;

Ron Huemoeller, Gilbert, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/552 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5387 (2013.01); H01L 23/552 (2013.01); H01L 25/0652 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01);
Abstract

In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein.


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