The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jun. 09, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eunkyul Oh, Gwacheon-si, KR;

Yunrae Cho, Guri-si, KR;

Taeheon Kim, Asan-si, KR;

Seunghun Han, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/78 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 21/66 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/565 (2013.01); H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 22/32 (2013.01); H01L 23/481 (2013.01); H01L 24/14 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/14517 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06596 (2013.01);
Abstract

The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.


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