The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2022
Filed:
Jul. 07, 2017
Intel Corporation, Santa Clara, CA (US);
Jack Z. Yinger, San Jose, CA (US);
Andrew Ling, Toronto, CA;
Tomasz Czajkowski, Toronto, CA;
Davor Capalija, Toronto, CA;
Eriko Nurvitadhi, San Jose, CA (US);
Deborah Marr, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Matrix multiplication systolic array feed methods and related processing element (PE) microarchitectures for efficiently implementing systolic array generic matrix multiplier (SGEMM) in integrated circuits is provided. A systolic array architecture may include a processing element array, a column feeder array, and a row feeder array. A bandwidth of external memory may be reduced by a factor of reduction based on interleaving of the matrix data via a feeding pattern of the column feeder array and the row feeder array.