The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Jan. 13, 2017
Applicant:

Transphorm Technology, Inc., Goleta, CA (US);

Inventors:

Carl Joseph Neufeld, Goleta, CA (US);

Mo Wu, Goleta, CA (US);

Toshihide Kikkawa, Goleta, CA (US);

Umesh Mishra, Montecito, CA (US);

Xiang Liu, Santa Barbara, CA (US);

David Michael Rhodes, Santa Barbara, CA (US);

John Kirk Gritters, Santa Barbara, CA (US);

Rakesh K. Lal, Isla Vista, CA (US);

Assignee:

Transphorm Technology, Inc., Goleta, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/324 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/517 (2013.01); H01L 21/02145 (2013.01); H01L 21/02271 (2013.01); H01L 21/28264 (2013.01); H01L 21/3245 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42364 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01);
Abstract

A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous AlSiO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.


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