The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Aug. 28, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Hokuto Kodate, Nagoya, JP;

Hiroyuki Ogawa, Nagoya, JP;

Dai Iwata, Yokkaichi, JP;

Mitsuhiro Togo, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/423 (2006.01); H01L 49/02 (2006.01); H01L 27/06 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42364 (2013.01); H01L 27/0629 (2013.01); H01L 28/24 (2013.01); H01L 28/75 (2013.01); H01L 28/91 (2013.01); H01L 28/92 (2013.01); H01L 29/401 (2013.01); H01L 29/4236 (2013.01);
Abstract

At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.


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