The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Oct. 15, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Raza Imam, Ghaziabad, IN;

Naveen Kumar, Distt.-Jhajjar, IN;

Shreyans Jain, Delhi, IN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/823475 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01);
Abstract

An integrated grid cell on an integrated circuit (IC) is disclosed. The integrated grid cell corresponds to at least one of an integrated one-grid cell and an integrated two-grid cell. The integrated grid cell includes various polysilicon layers, metal-0 oxide diffusion (M0OD) layers, and a metal-0 polysilicon (M0PO) layer. The polysilicon layers, the M0OD layers, and the M0PO layer are formed such that potential differences are created between one or more polysilicon layers and one or more M0OD layers. Such potential differences between the one or more polysilicon layers and the one or more M0OD layers lead to formation of various parasitic capacitors between the one or more polysilicon layers and the one or more M0OD layers. The parasitic capacitors correspond to decoupling capacitors that mitigate a dynamic IR drop and a supply noise associated with the IC.


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