The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Dec. 18, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jimin Yao, Chandler, AZ (US);

Kyle Yazzie, Chandler, AZ (US);

Shawna M. Liff, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H05K 3/10 (2006.01); B29C 70/68 (2006.01); H01L 21/48 (2006.01); H01L 23/544 (2006.01); H01L 23/58 (2006.01); H01L 23/14 (2006.01); B29L 31/34 (2006.01); B29K 63/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); B29C 70/68 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/544 (2013.01); H01L 23/585 (2013.01); H05K 3/108 (2013.01); B29K 2063/00 (2013.01); B29L 2031/3481 (2013.01); H01L 23/145 (2013.01); H01L 2223/54426 (2013.01);
Abstract

An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.


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