The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Dec. 23, 2020
Applicant:

Sj Semiconductor (Jiangyin) Corporation, JiangYin, CN;

Inventors:

Chengtar Wu, JiangYin, CN;

Yenheng Chen, JiangYin, CN;

Chengchung Lin, JiangYin, CN;

Yayuan Xue, JiangYin, CN;

Han Xu, JiangYin, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/22 (2006.01); H01Q 1/22 (2006.01); H01Q 1/40 (2006.01); H01Q 21/00 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/2283 (2013.01); H01Q 1/40 (2013.01); H01Q 21/0087 (2013.01);
Abstract

The present disclosure provides an antenna packaging structure and a method for forming the same. The structure includes: a supporting substrate, a rewiring layer on the supporting substrate, a first antenna layer disposed on the rewiring layer, first metal feedline pillars disposed on the first antenna layer, a first packaging layer covering the first metal feedline pillars except exposing the top surfaces of the first metal feedline pillars; a second antenna layer on the first packaging layer, second metal feedline pillars, a second packaging layer covering the second metal feedline pillars except exposing the top surfaces of the second metal feedline pillars; a third antenna layer disposed on the second packaging layer, semiconductor chips connected to the rewiring layer, a metal bump disposed inside an opening in the rewiring layer, and a third packaging layer encapsulating the semiconductor chips and the metal bump.


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