The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Dec. 02, 2020
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Chung-Hsuan Wang, Taichung, TW;

Yu-Ting Chen, Taichung, TW;

Tz-Hau Guo, Taichung, TW;

Chang-Hsuan Wu, Taichung, TW;

Chiung-Lin Hsu, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1206 (2013.01); H01L 27/2409 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/1246 (2013.01); H01L 45/16 (2013.01);
Abstract

Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.


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