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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11316047 B1

PDFFull Text
Date of Patent:
Apr. 26, 2022

Filed:

Oct. 24, 2019

Structure and formation method of semiconductor device with monoatomic etch stop layer

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Ting Ko, Kaohsiung, TW;

Bo-Cyuan Lu, New Taipei, TW;

Jr-Hung Li, Chupei, TW;

Chi-On Chui, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Stephen M Bradley

Assistant Examiner:

Gustavo G Ramallo

Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 23/535 (2006.01); H01L 29/04 (2006.01); H01L 29/165 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/022 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02211 (2013.01); H01L 21/02247 (2013.01); H01L 21/02252 (2013.01); H01L 21/76829 (2013.01); H01L 23/535 (2013.01); H01L 29/04 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.

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