The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2022
Filed:
Aug. 09, 2018
Applicant:
Namics Corporation, Niigata, JP;
Inventors:
Assignee:
NAMICS CORPORATION, Niigata, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/29 (2006.01); H01L 23/24 (2006.01); H01L 23/31 (2006.01); H01L 23/433 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/29 (2013.01); H01L 23/24 (2013.01); H01L 23/3121 (2013.01); H01L 23/3142 (2013.01); H01L 23/4334 (2013.01); H01L 24/73 (2013.01); H01L 24/743 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/181 (2013.01);
Abstract
An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor deviceincludes a semiconductor chipand a substratethat are molded with a mold resin layerThe semiconductor deviceincludes a resin layerhaving a thickness of 200 nm or less different from the mold resin layerbetween the cured mold resin layerand the substrateThe resin layerpresent between the mold resin layerand the substrateis preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.