The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2022

Filed:

Jun. 19, 2019
Applicant:

Disco Corporation, Tokyo, JP;

Inventor:

Jinyan Zhao, Tokyo, JP;

Assignee:

DISCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/46 (2006.01); H01L 21/78 (2006.01); B23K 26/364 (2014.01); B23K 26/40 (2014.01); H01L 21/683 (2006.01); C09J 7/24 (2018.01); H01L 21/304 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); B23K 26/364 (2015.10); B23K 26/40 (2013.01); C09J 7/241 (2018.01); H01L 21/3043 (2013.01); H01L 21/6836 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01);
Abstract

A wafer processing method includes a sheet bonding step of placing a polyolefin or polyester sheet on a front side of a wafer having a device area where devices are formed so as to be separated by division lines, the sheet having a size capable of covering the device area, and next performing thermocompression bonding to bond the sheet to the front side of the wafer, thereby protecting the front side of the wafer with the sheet. The method further includes a test element group (TEG) cutting step of applying a first laser beam through the sheet to the wafer along each division line thereby cutting a TEG formed on each division line, and a modified layer forming step of applying a second laser beam to a back side of the wafer along each division line, the second laser beam having a transmission wavelength to the wafer, thereby forming a modified layer inside the wafer along each division line.


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