The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2022
Filed:
Nov. 14, 2019
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Wei-Hao Wu, Hsinchu, TW;
Zhi-Chang Lin, Zhubei, TW;
Ting-Hung Hsu, MiaoLi, TW;
Kuan-Lun Cheng, Hsin-chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 27/092 (2006.01); B82Y 10/00 (2011.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/775 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 29/08 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); B82Y 10/00 (2013.01); H01L 21/762 (2013.01); H01L 21/76224 (2013.01); H01L 21/8221 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823828 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/1211 (2013.01); H01L 27/1248 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/78654 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01); H01L 29/66469 (2013.01);
Abstract
A semiconductor device includes a first device formed over a substrate. The first device includes a first gate stack encircling a first nanostructure, and the first device is a logic circuit device. The semiconductor device includes a second device formed over the first device. The second device includes a second gate stack encircling a second nanostructure, and the second device is a static random access memory (SRAM).