The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Jul. 06, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Tung-Jiun Wu, Hsinchu County, TW;

Yinlung Lu, Hsinchu, TW;

Mingni Chang, Hsinchu, TW;

Ming-Yih Wang, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/76804 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/5223 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 28/60 (2013.01); H01L 2224/0219 (2013.01); H01L 2224/02181 (2013.01); H01L 2224/03011 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/13026 (2013.01); H01L 2224/13147 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/3512 (2013.01);
Abstract

A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.


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