The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2022
Filed:
Dec. 18, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Chia-Min Lin, Hsinchu, TW;
Ching-Hua Hsieh, Hsinchu, TW;
Chih-Wei Lin, Hsinchu County, TW;
Sheng-Hsiang Chiu, Tainan, TW;
Sheng-Feng Weng, Taichung, TW;
Yao-Tong Lai, Yilan County, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.