The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Mar. 01, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ya-Huei Li, Hsinchu, TW;

Li-Wei Chu, Hsinchu, TW;

Yu-Hsiang Liao, Hsinchu, TW;

Hung-Yi Huang, Hsinchu, TW;

Chih-Wei Chang, Hsinchu, TW;

Ching-Hwanq Su, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/66 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76846 (2013.01); H01L 21/76883 (2013.01); H01L 21/76889 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53209 (2013.01); H01L 23/53266 (2013.01); H01L 21/0274 (2013.01); H01L 21/31116 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 29/665 (2013.01);
Abstract

A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.


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