The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Aug. 29, 2019
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Chih-Jung Ni, Taichung, TW;

Chuan-Chi Chou, Hsinchu, TW;

Yao-Ting Tsai, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 5/063 (2013.01); H01L 27/11526 (2013.01);
Abstract

The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.


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