The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2022

Filed:

Aug. 22, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chin-Fu Kao, Taipei, TW;

Chih-Yuan Chien, Hsinchu County, TW;

Li-Hui Cheng, New Taipei, TW;

Szu-Wei Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4853 (2013.01); H01L 21/568 (2013.01); H01L 23/3121 (2013.01); H01L 23/367 (2013.01); H01L 23/5389 (2013.01); H01L 24/32 (2013.01); H01L 21/561 (2013.01); H01L 2224/32055 (2013.01); H01L 2225/0652 (2013.01);
Abstract

Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.


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