The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Dec. 23, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rohan K. Bambery, Hillsboro, OR (US);

Walid M. Hafez, Portland, OR (US);

Mong-Kai Wu, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/823821 (2013.01); H01L 23/5256 (2013.01);
Abstract

Metal fuses and self-aligned gate edge (SAGE) architectures having metal fuses are described. In an example, an integrated circuit structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal fuse is on the gate edge isolation structure.


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