The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2022
Filed:
Sep. 26, 2019
Intel Corporation, Santa Clara, CA (US);
Richard Vreeland, Beaverton, OR (US);
Colin Carver, Hillsboro, OR (US);
William Brezinski, Beaverton, OR (US);
Michael Christenson, Hillsboro, OR (US);
Nafees Kabir, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.