The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Sep. 25, 2020
Applicant:

The 13th Research Institute of China Electronics Technology Group Corporation, Shijiazhuang, CN;

Inventors:

Xingye Zhou, Shijiazhuang, CN;

Zhihong Feng, Shijiazhuang, CN;

Yuanjie Lv, Shijiazhuang, CN;

Xin Tan, Shijiazhuang, CN;

Yuangang Wang, Shijiazhuang, CN;

Xubo Song, Shijiazhuang, CN;

Jia Li, Shijiazhuang, CN;

Yulong Fang, Shijiazhuang, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 31/18 (2006.01); H01L 31/06 (2012.01); H01L 31/103 (2006.01); H01L 31/0352 (2006.01); H01L 21/02 (2006.01); C01B 32/956 (2017.01);
U.S. Cl.
CPC ...
H01L 31/1812 (2013.01); H01L 21/02378 (2013.01); H01L 31/03529 (2013.01); H01L 31/035281 (2013.01); H01L 31/06 (2013.01); H01L 31/1037 (2013.01); C01B 32/956 (2017.08);
Abstract

The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.


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