The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Nov. 15, 2018
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Roman Gouk, San Jose, CA (US);

Giback Park, San Jose, CA (US);

Kyuil Cho, Santa Clara, CA (US);

Han-Wen Chen, Cupertino, CA (US);

Chintan Buch, Sunnyvale, CA (US);

Steven Verhaverbeke, San Francisco, CA (US);

Vincent Dicaprio, Pleasanton, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/038 (2006.01); G03F 7/00 (2006.01); H01L 21/768 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
G03F 7/0002 (2013.01); G03F 7/0035 (2013.01); G03F 7/2004 (2013.01); H01L 21/768 (2013.01);
Abstract

A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.


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