The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2022
Filed:
Sep. 02, 2020
Tokyo Electron Limited, Tokyo, JP;
Jeffrey Smith, Clifton Park, NY (US);
Hiroaki Niimi, Cohoes, NY (US);
Jodi Grzeskowiak, Schenectady, NY (US);
Daniel Chanemougame, Niskayuna, NY (US);
Lars Liebmann, Mechanicsville, NY (US);
Kandabara Tapily, Mechanicsville, NY (US);
Subhadeep Kal, Albany, NY (US);
Anton J. deVilliers, Clifton Park, NY (US);
Tokyo Electron Limited, Tokyo, JP;
Abstract
A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.