The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2022
Filed:
May. 22, 2020
Intel Corporation, Santa Clara, CA (US);
Abhishek R. Appu, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
James A. Valerio, Hillsboro, OR (US);
Altug Koker, El Dorado Hills, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
Balaji Vembu, Folsom, CA (US);
Wenyin Fu, Folsom, CA (US);
Bhushan M. Borole, Rancho Cordova, CA (US);
Kamal Sinha, Rancho Cordova, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.