The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Mar. 20, 2018
Applicant:

Toyo Tanso Co., Ltd., Osaka, JP;

Inventors:

Satoshi Torimi, Kanonji, JP;

Yusuke Sudo, Kanonji, JP;

Masato Shinohara, Kanonji, JP;

Youji Teramoto, Kanonji, JP;

Takuya Sakaguchi, Kanonji, JP;

Satoru Nogami, Kanonji, JP;

Makoto Kitabatake, Kanonji, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C30B 25/18 (2006.01); C30B 29/36 (2006.01); H01L 29/34 (2006.01); H01L 29/16 (2006.01); C30B 25/20 (2006.01);
U.S. Cl.
CPC ...
C30B 25/186 (2013.01); C30B 25/20 (2013.01); C30B 29/36 (2013.01); H01L 21/0243 (2013.01); H01L 21/0262 (2013.01); H01L 21/02378 (2013.01); H01L 21/02529 (2013.01); H01L 29/1608 (2013.01); H01L 29/34 (2013.01);
Abstract

In a method for manufacturing a reformed SiC wafer(a surface treatment method for a SiC wafer) having its surface that is reformed by processing an untreated SiC waferbefore formation of an epitaxial layerthe method includes a surface reforming step as described below. That is, the untreated SiC waferincludes BPDs as dislocations parallel to an inside of a (0001) face, and TEDs. Property of the surface of the untreated SiC waferis changed so as to have higher rate in which portions having BPDs on the surface of the untreated SiC waferpropagate as TEDs at a time of forming the epitaxial layer


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