The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Jul. 01, 2020
Applicant:

Nexchip Semiconductor Co., Ltd, Anhui, CN;

Inventors:

Yongbo Feng, Anhui, CN;

Hongbo Zhu, Anhui, CN;

Houyou Wang, Anhui, CN;

Mingyang Tsai, Anhui, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02126 (2013.01); H01L 21/823462 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01);
Abstract

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate includes a first region and a second region; forming a first polycrystalline silicon layer on the substrate, wherein the first polycrystalline silicon layer covers the first region and the second region; forming a stacked structure on the first polycrystalline silicon layer; forming a protective layer on the stacked structure; forming a patterned photoresist layer on the protective layer, wherein the patterned photoresist layer exposes the protective layer in the second region; removing the protective layer and the stacked structure in the second region to expose the first polycrystalline silicon layer in the second region; removing the patterned photoresist layer; and forming a second polycrystalline silicon layer on the protective layer in the first region and the first polycrystalline silicon layer in the second region.


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