The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Jul. 24, 2019
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Jian-Ting Chen, Tainan, TW;

Yao-Ting Tsai, Kaohsiung, TW;

Jung-Ho Chang, Yunlin County, TW;

Hsiu-Han Liao, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 27/11521 (2017.01); H01L 27/11531 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/3215 (2006.01); H01L 21/311 (2006.01); H01L 29/788 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/40114 (2019.08); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/32155 (2013.01); H01L 27/11521 (2013.01); H01L 27/11531 (2013.01); H01L 29/42324 (2013.01); H01L 29/4916 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.


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