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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11251069 B1

PDFFull Text
Date of Patent:
Feb. 15, 2022

Filed:

Sep. 11, 2020

Method for forming isolation with multi-step structure

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ta-Chun Lin, Hsinchu, TW;

Tien-Shao Chuang, Hsinchu, TW;

Kuang-Cheng Tai, Hsinchu, TW;

Chun-Hung Chen, Hsinchu, TW;

Chih-Hung Hsieh, Hsin-Chu, TW;

Kuo-Hua Pan, Hsinchu, TW;

Jhon-Jhy Liaw, Zhudong Township, Hsinchu County, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Daniel P Shook

Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76232 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.

Find Patent Forward Citations

Lin, Ta-Chun. (2022). Method for forming isolation with multi-step structure (U.S. Patent No. 11251069). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11251069

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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