The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Sep. 13, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Markus Bina, Sauerlach, DE;

Hans-Joachim Schulze, Taufkirchen, DE;

Werner Schustereder, Villach, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G21G 1/06 (2006.01); H01L 21/261 (2006.01); C30B 31/20 (2006.01); G21G 4/02 (2006.01);
U.S. Cl.
CPC ...
G21G 1/06 (2013.01); C30B 31/20 (2013.01); H01L 21/261 (2013.01); G21G 4/02 (2013.01);
Abstract

An apparatus for processing a plurality of semiconductor wafers, the apparatus including a spallation chamber, a neutron producing material mounted in the spallation chamber, a neutron moderator, and an irradiation chamber coupled to the spallation chamber, wherein the neutron moderator is disposed between the spallation chamber and the irradiation chamber, wherein the irradiation chamber is configured to accommodate the plurality of semiconductor wafers, wherein each of the plurality of semiconductor wafers has a first surface and a second surface opposite the first surface, wherein the plurality of semiconductor wafers are positioned so that a first surface of one semiconductor wafer faces a second surface of another semiconductor wafer.


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