The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Sep. 26, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

R Selvakumar Raja Gopal, Tapah, MY;

Asad Azam, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/76 (2013.01); H04L 9/06 (2006.01); G06F 21/60 (2013.01); G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G06F 21/44 (2013.01);
U.S. Cl.
CPC ...
G06F 21/76 (2013.01); G01R 31/3177 (2013.01); G01R 31/31713 (2013.01); G06F 21/44 (2013.01); G06F 21/606 (2013.01); H04L 9/0631 (2013.01);
Abstract

Various systems and methods for implementing secure system-on-chip (SoC) debugging are described herein. A method of providing secure system-on-a-chip (SoC) debugging, comprises: receiving, from a remote host at a debug companion circuit, a debug initiation request to initiate a debugging session with an SoC associated with the debug companion circuit; encrypting, at the debug companion circuit, a debug handshake command; transmitting the debug handshake command to the SoC from the debug companion circuit, wherein the SoC is configured to authenticate the debug companion circuit, and configure intellectual property (IP) blocks on the SoC to expose debug data to the debug companion circuit in response to authenticating the debug companion circuit; and managing a secure connection with the SoC to obtain debug data and report the debug data to the remote host.


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