The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2022
Filed:
Apr. 09, 2020
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
National Taiwan University, Taipei, TW;
National Taiwan Normal University, Taipei, TW;
Tung-Ying Lee, Hsinchu, TW;
Tse-An Chen, Taoyuan, TW;
Tzu-Chung Wang, Hsinchu, TW;
Miin-Jang Chen, Taipei, TW;
Yu-Tung Yin, Taipei, TW;
Meng-Chien Yang, Taoyuan, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
NATIONAL TAIWAN UNIVERSITY, Taipei, TW;
NATIONAL TAIWAN NORMAL UNIVERSITY, Taipei, TW;
Abstract
A method of manufacturing a semiconductor device includes forming a fin structure comprising alternately stacked first semiconductor layers and second semiconductor layers over a substrate. A sacrificial gate structure is formed over the fin structure. Spacers are formed on either side of the sacrificial gate structure. The sacrificial gate structure is removed to form a trench between the spacers. The first semiconductor layers are removed from the trench, while leaving the second semiconductor layers suspended in the trench. A self-assembling monolayer is formed on sidewalls of the spacers in the trench. Interfacial layers are formed encircling the suspended second semiconductor layers, respectively. A high-k dielectric layer is deposited at a faster deposition rate on the interfacial layers than on the self-assembling monolayer. A metal gate structure is formed over the high-k dielectric layer.