The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Mar. 30, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyuekjae Lee, Hwaseong-si, KR;

Jihoon Kim, Asan-si, KR;

Jihwan Suh, Cheonan-si, KR;

Soyoun Lee, Hwaseong-si, KR;

Jiseok Hong, Yongin-si, KR;

Taehun Kim, Asan-si, KR;

Jihwan Hwang, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/16 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/16 (2013.01); H01L 23/31 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01);
Abstract

Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.


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