The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Apr. 28, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-Tung Hsu, Taoyuan, TW;

Chang-Cheng Hung, Hsinchu County, TW;

Tyrone Kuo, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01); G06F 1/16 (2006.01); G09G 3/20 (2006.01); G06F 1/18 (2006.01); G09F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 1/1652 (2013.01); G06F 1/189 (2013.01); G09F 9/301 (2013.01); G09G 3/20 (2013.01); G09G 2300/0426 (2013.01); G09G 2380/02 (2013.01);
Abstract

A semiconductor package includes a flexible substrate and a semiconductor device. The flexible substrate includes a device bonding region and a device top metallization structure including a plurality of device signal lines and a plurality of device power lines extended beyond the device bonding region. The semiconductor device is disposed on the device bonding region and includes an interconnecting metallization structure and a passivation layer covering the interconnecting metallization structure and revealing a plurality of interconnect contacts of the interconnecting metallization structure, wherein the plurality of interconnect contacts electrically connected to one another through the device top metallization structure.


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