The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Nov. 27, 2019
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Sylvain Barraud, Grenoble, FR;

Joris Lacord, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 29/42392 (2013.01); H01L 29/66484 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/7855 (2013.01); H01L 29/7856 (2013.01); H01L 29/78648 (2013.01);
Abstract

A method for producing an FET transistor includes producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; and producing a second gate in the second gate location and against the second side face of the channel.


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