The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Feb. 03, 2020
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Shiv Kumar Mishra, Mechanicville, NY (US);

Baofu Zhu, Clifton Park, NY (US);

Arkadiusz Malinowski, Malta, NY (US);

Kaushikee Mishra, Malta, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. INC., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/26 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/266 (2006.01); H01L 21/74 (2006.01); H01L 21/762 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0653 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/74 (2013.01); H01L 21/76229 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/66681 (2013.01); H01L 29/66795 (2013.01); H01L 29/7816 (2013.01); H01L 29/7851 (2013.01);
Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.


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