The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Jul. 13, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jean-Pierre Colinge, Hsinchu, TW;

Carlos H. Diaz, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/465 (2006.01); H01L 21/306 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 21/30604 (2013.01); H01L 21/465 (2013.01); H01L 29/41791 (2013.01); H01L 29/456 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.


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