The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Jul. 22, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Alexander Hoefler, Austin, TX (US);

Glenn Charles Abeln, Buda, TX (US);

Brad John Garni, Austin, TX (US);

Nihaar N. Mahatme, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); H04L 9/32 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
H04L 9/3278 (2013.01);
Abstract

A physically unclonable function (PUF) includes an array of differential PUF bits arranged in rows and columns, wherein each differential bit is located at an intersection of a row and a column, and includes a first PUF cell coupled to a corresponding first bit line and first source line and a second PUF cell coupled to a corresponding second bit line and second source line. The PUF includes a source bias transistor coupled between each corresponding first source line and a first power supply terminal and between each corresponding second source line and the first power supply terminal, wherein a gate electrode of each of the source bias transistors is coupled to a second power supply terminal, and a corresponding set of margin transistors coupled in parallel with each source bias transistor, wherein a gate electrode of each margin transistor is coupled to receive a corresponding margin setting control signal.


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