The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

May. 01, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sean D. Burns, Hopewell Junction, NY (US);

Lawrence A. Clevenger, Rhinebeck, NY (US);

Nelson M. Felix, Briarcliff Manor, NY (US);

Sivananda K. Kanakasabapathy, Niskayuna, NY (US);

Christopher J. Penny, Saratoga Springs, NY (US);

Nicole Saulnier, Albany, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01);
Abstract

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.


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