The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Sep. 16, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chi-Hsing Hsu, New Taipei, TW;

Sai-Hooi Yeong, Zhubei, TW;

Ching-Wei Tsai, Hsinchu, TW;

Kuan-Lun Cheng, Hsin-Chu, TW;

Chih-Hao Wang, Baoshan Township, TW;

Min Cao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02186 (2013.01); H01L 21/02189 (2013.01); H01L 21/02194 (2013.01); H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/517 (2013.01);
Abstract

A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.


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