The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Jan. 24, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Gregory S. Mathews, Saratoga, CA (US);

Kai Lun Hsiung, Fremont, CA (US);

Lakshmi Narasimha Murthy Nukala, Pleasanton, CA (US);

Peter Fu, Saratoga, CA (US);

Rakesh L. Notani, Santa Clara, CA (US);

Sukalpa Biswas, Fremont, CA (US);

Thejasvi Magudilu Vijayaraj, San Jose, CA (US);

Yanzhe Liu, Sunnyvale, CA (US);

Shane J. Keil, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0611 (2013.01); G06F 3/0673 (2013.01);
Abstract

Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.


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