The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Sep. 30, 2019
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Tomohide Terashima, Tokyo, JP;

Yasuhiro Kagawa, Tokyo, JP;

Kensuke Taguchi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/22 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/32 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 21/221 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/32 (2013.01); H01L 29/66068 (2013.01); H01L 29/7395 (2013.01); H01L 29/7804 (2013.01); H01L 29/7815 (2013.01);
Abstract

There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.


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