High speed memory device implementing a plurality of supply voltages

Abstract

Embodiments herein include a first line, wherein the first line is complementary to a second line; a voltage generator configured to generate a first supply voltage, a second supply voltage and a third supply voltage, the third supply voltage is lower than the second supply voltage, the voltage generator further comprises a transistor structure with a plurality of transistors electrically connected in parallel from the first supply voltage to a supply output node that provides the second supply voltage; a memory cell electrically coupled to the first and second lines, the memory cell further comprises two cross-coupled transistor strings connected from the first supply voltage to a ground voltage; a pre-charger with a first pre-charger transistor cross-coupled to a second pre-charger transistor, the pre-charger is configured to pre-charge the first and second lines to a level of a source voltage.