The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Jan. 05, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Hsien Tsai, Taoyuan County, TW;

Ya-Tin Chang, Hsinchu, TW;

Ruey-Bin Sheen, Taichung, TW;

Chih-Hsien Chang, New Taipei, TW;

Cheng-Hsiang Hsieh, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/081 (2006.01); H03L 7/095 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0814 (2013.01); H03L 7/0818 (2013.01); H03L 7/095 (2013.01);
Abstract

Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.


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