The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2021
Filed:
Jul. 26, 2019
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventor:
Arup Bhattacharyya, Essex Junction, VT (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/1157 (2017.01); H01L 29/66 (2006.01); G11C 17/12 (2006.01); H01L 21/28 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01); H01L 29/423 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 29/7923 (2013.01); G11C 16/0475 (2013.01); G11C 16/16 (2013.01); G11C 17/123 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); H01L 29/40117 (2019.08); H01L 29/42348 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01);
Abstract
In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.