The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Mar. 11, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Tsukasa Tokutomi, Kamakura, JP;

Masanobu Shirakawa, Chigasaki, JP;

Takuya Futatsuyama, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11578 (2017.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11578 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: first and second memory cells; a first and second word lines; and a first bit line. The device is configured to execute first to sixth operations. In the first operation, a first voltage is applied to the first word line and a second voltage is applied to a semiconductor layer. In the second operation, the first voltage is applied to the second word line. In the third operation, a third voltage is applied to the first word line. In the fourth operation, the third voltage is applied to the second word line. In the fifth operation, a fourth voltage is applied to the first word line. In the sixth operation, the fourth voltage is applied to the second word line.


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