The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2021
Filed:
Jun. 02, 2020
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Shih-Fan Kuan, Taoyuan, TW;
Yi-Jen Lo, New Taipei, TW;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 21/82 (2006.01); H01L 21/768 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 24/09 (2013.01); H01L 21/4846 (2013.01); H01L 21/76877 (2013.01); H01L 21/82 (2013.01); H01L 23/3114 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/17 (2013.01); H01L 23/49816 (2013.01); H01L 23/525 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0237 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/11 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/81 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2924/014 (2013.01);
Abstract
A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.