The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2021
Filed:
Jan. 15, 2021
Synopsys, Inc., Mountain View, CA (US);
Kelvin Le, Mountain View, CA (US);
Wenwen Chai, Mountain View, CA (US);
Li Ding, Mountain View, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
Embodiments provide for mitigating parametric yield loss of an integrated circuit (IC) design. In certain embodiments, a delay distribution associated with at least one cell disposed in the design is determined. A pin slack distribution associated with paths in which the at least one cell is disposed is determined. A residual distribution is determined based at least in part on the delay distribution and the pin slack distribution. Yield loss associated with the at least one cell is determined based at least in part on the delay distribution and the residual distribution. When it is determined that that the yield loss associated with the at least one cell exceeds a yield loss threshold, the at least one cell may be identified as a candidate for replacement with a replacement cell.